Reliability-Based Optimization of Spin-Transfer Torque Magnetic Tunnel Junction Implication Logic Gates

Recently, magnetic tunnel junction (MTJ)-based implication logic gates have been proposed to realize a fundamental Boolean logic operation called material implication (IMP). For given MTJ characteristics, the IMP gate circuit parameters must be optimized to obtain the minimum IMP error probability. In this work we present the optimization method and investigate the effect of MTJ device parameters on the reliability of IMP logic gates. It is shown that the most important MTJ device parameters are the tunnel magnetoresistance (TMR) ratio and the thermal stability factor ∆. The IMP error probability decreases exponentially with increasing TMR and ∆. Introduction Material implication (a IMP b reads ‘a implies b’ or ‘if a, then b’) [1] is one of the four fundamental Boolean logic operations like AND, OR, NOT and is equivalent to ‘(NOT a) OR b’ as shown in Table I. However, IMP has been seldomly discussed in modern digital electronics as Shannon introduced switching algebra based on the latter three operations [2]. These operations can be easily realized using switching devices, e.g., two switches connected in parallel (series) can mimic the AND (OR) logic function and form a computationally complete logic basis needed to reproduce arbitrary Boolean functions. Recently, the realization of the IMP operation has been demonstrated [3] in a simple circuit with two TiO2 memristors [4] and a common resistor. Using the non-volatile memristive elements as the main element for the logic computations (logic gate) intrinsically provides a non-volatile logic-in-memory architecture (called “Stateful” logic) and circumvents the leakage power issue which has become an important obstacle for scaling CMOS [5, 6, 7]. However, the TiO2-based IMP logic requires a different fabrication platform than the existing cost-effective silicon process and provides only low operation speed. In contrast to [3], we investigated magnetic tunnel junctions (MTJs) as the non-volatile memorizing elements to build spintronic-based IMP gates, and we proposed a new topology driven by a current source, which offers a more energy-efficient and reliable logic implementation than the standard topology with a common resistor [8, 9]. In previously proposed MTJ-based logic-inmemory architectures the MTJs are only used for storing binary data [10]; they require CMOSbased logic units and/or sensing amplifiers [11]. However, the MTJ-based implication logic uses the MTJs also as the main devices for logic computations and is suited for large-scale non-volatile logic-in-memory applications [12, 13]. Therefore, it enables intrinsic non-volatile logic circuits decreasing the device count and power consumption, and it increases logic density and operation speed simultaneously. Here we describe a reliability-based optimization scheme for the circuit and device parameters in the current-controlled IMP logic circuits. Table I: Material implication (IMP) truth table. a b a IMP b 0 0 1 0 1 1 1 0 0 1 1 1 Advanced Materials Research Vol. 854 (2014) pp 89-95 © (2014) Trans Tech Publications, Switzerland doi:10.4028/www.scientific.net/AMR.854.89